1. Field of the Invention
This invention relates generally to processes for fabricating semiconductor devices in integrated circuits, and to processes for doping the substrate beneath the field regions in CMOS integrated circuits. Most specifically the invention relates to a process for doping the silicon beneath the field isolation regions in CMOS integrated circuits in a manner compatible with conventional n-MOS process technology.
2. Description of the Prior Art
Complementary metal-oxide-silicon devices (known as "CMOS") are integrated circuits in which both n-MOS and p-MOS transistors are formed in a single substrate. If the circuits are fabricated in a n-type substrate, then a p-channel transistor is made in a conventional manner, but an n-channel transistor requires an island of p-type material. In the fabrication of CMOS devices, the p-conductivity type wells (or n-type wells if a p substrate is used) must be electrically isolated from the surrounding substrate. In conventional CMOS processes this isolation is achieved by formation of a relativiely thick layer of oxidized silicon around the periphery of the p-well and extending into the substrate. To prevent channel inversion, selected conductivity type impurity is typically introduced into the silicon substrate to form a doped region beneath the field oxide regions. In the prior art this doped region, often termed the "field implant," typically has been achieved in one of two ways. According to a first process, for example, as shown and described in U.S. Pat. No. 4,306,916 to Wollesen et al., a low energy implant is used to form a doped region beneath the field oxide. The single implant relies upon the masking properties of the composite layer of silicon dioxide and silicon nitride to shield underlying regions of the wafer where a lesser impurity concentration is desired. In an alternate embodiment, a two-step process is used to dope both the p-well and the regions beneath the field oxide.
An alternative way of fabricating field implants in such a structure is described in "Silicon-Gate N-Well CMOS Process by Full Ion-Implantation Technology," by T. Ohzone et al. published in IEEE Transactions on Electron Devices, Volume Ed-27, No. 9, September 1980, at page 1789. The process described relies upon a double layer of photoresist to provide appropriate impurity concentrations in both the wells and beneath the field oxide regions.
Unfortunately, both of the above processes are difficult to control, and are not compatible with standard n-MOS process lines. Compatibility with standard n-MOS process lines is highly advantageous in commercial semiconductor operations because such compatibility eliminates the need to establish separate processing facilities for the initial fabrication steps in the manufacture of CMOS devices. Of course, difficulty in controlling the processes of the prior art results in lower yields and lesser quality products than that achievable with processes which are more readily controlled.